1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a carrier-free semiconductor package and a fabrication method thereof.
2. Description of Related Art
To meet consumer demands for convenience and portability, electronic products are becoming much lighter, thinner, shorter and smaller. In addition, electronic products are required to have high efficient performance, low power consumption and multi-function. Generally, semiconductor chips are mounted on packaging substrates and encapsulated so as to achieve high electrical performance However, the packaging substrates increase the overall thickness of final packages.
Accordingly, US Patent Application Publication No. 20080145967 discloses a carrier-free semiconductor package and a fabrication method thereof, as shown in FIGS. 1A to 1H.
Referring to FIG. 1A, a carrier 10 is provided.
Referring to FIG. 1B, a resist layer 11 is formed on the carrier 10 and a plurality of openings 110 are formed in the resist layer 11 for exposing portions of the carrier 10.
Referring to FIG. 1C, by using the carrier 10 as a current conductive path for electroplating, conductive traces 12 are formed on the portions of the carrier 10 in the openings 110 of the resist layer 11.
Referring to FIG. 1D, the resist layer 11 is removed to expose the carrier 10 and the conductive traces 12 on the carrier 10.
Referring to FIG. 1E, a mold 13 is disposed on the carrier 10. The mold 13 has a mold cavity 130, and a plurality of protrusions 131 that abut against the conductive traces 12, respectively.
Referring to FIG. 1F, an insulating material is injected into the mold cavity 130 so as to form an insulating layer 14 in the mold cavity 130. Meanwhile, a plurality of openings 140 are formed at positions corresponding to the protrusions 131.
Referring to FIG. 1G, the mold 13 and the carrier 10 are removed such that the conductive traces 12 are embedded in the insulating layer 14. Bottom surfaces of the conductive traces 12 are exposed through a bottom surface of the insulating layer 14 while top surfaces of the conductive traces 12 are exposed through the openings 140, respectively.
Referring to FIG. 1H, a plurality of solder balls 15 are disposed on the top surfaces of the conductive traces 12 in the openings 140, and a chip 16 is electrically connected to the bottom surfaces of the conductive traces 12 exposed through the bottom surface of the insulating layer 14, thus forming a carrier-free semiconductor package.
However, the above-described single-layer carrier-free package is difficult to be applied in RF (radio frequency) field, since a ground design is required for the characteristic impedance of a microstrip line and also a carrier such as a dielectric layer needs to be disposed between RF traces and the ground.
Therefore, there is a need to provide a carrier-free semiconductor package having an RF function and a fabrication method thereof.